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never stop thinking. hyb25d256[40/80/16]0ce(l) hyb25d256[40/80/16]0c[t/c/f] 256 mbit double-data-rate sdram data sheet, rev. 1.6, dec. 2004 memory products
edition 2004-12 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hyb25d256[40/80/16]0ce(l) hyb25d256[40/80/16]0c[t/c/f] 256 mbit double-data-rate sdram data sheet, rev. 1.6, dec. 2004 memory products
template: mp_a4_v1.0_2003-04-25.fm hyb25d256[40/80/16]0ce(l), hy b25d256[40/80/16]0c[t/c/f] revision history: rev. 1.6 2004-12 previous version: rev. 1.5 2004-11 19 , 20 , 21 editorial change we listen to your comments any information within this do cument that you feel is wro ng, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
data sheet 5 rev. 1.6, 2004-12 08012003-8754-paqx hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.2 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.3 read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2.4 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.1 dll enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.2 output drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5.1 bank/row activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5.2 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.5.3 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.4 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.5.5 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.5.6 input clock frequency change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.6 simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.2 normal strength pull-down and pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3 weak strength pull-down and pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.5 i dd current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.1 write command: data in put timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.2 read command: data output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3 initialization and mode register set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.4 power: power down mode command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.5 refresh: auto refresh mode command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.6 refresh: self refresh mode command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.7 read: without auto precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.8 read: with auto precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.9 read: bank read access command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.10 write: without auto precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.11 write: with auto precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.12 write: bank write access command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.13 write: dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6 system characteristics for ddr sdrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table of contents
data sheet 6 rev. 1.6, 2004-12 08012003-8754-paqx hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram figure 1 pin configuration p-tfbga-60-9 top view, see the balls throught the package . . . . . . . . . . . . . 17 figure 2 pin configuration p-tsopii-66-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 3 block diagram 16 mbit 4 i/o 4 internal memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4 block diagram 8 mbit 8 i/o 4 internal memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 5 block diagram 4 mbit 16 i/o 4 internal memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6 required cas latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 7 activating a specific row in a specific bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 8 t rcd and t rrd definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 9 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 10 read burst: cas latencies (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 11 consecutive read bursts: cas lat encies (burst length = 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12 non-consecutive read bu rsts: cas latencies (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 13 random read accesses: cas latencies (burst length = 2, 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . 37 figure 14 terminating a read burst: cas latencies (burst length = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 15 read to write: cas latencies (burst length = 4 or 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 16 read to precharge: cas latencies (burst length = 4 or 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 18 write burst (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 19 write to write (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 20 write to write: max. dqss, non- consecutive (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 21 random write cycles (burst length = 2, 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 22 write to read: non-interrupting (cas latency = 2; burs t length = 4). . . . . . . . . . . . . . . . . . . . . . 47 figure 23 write to read: interrupting (cas latency = 2; burst leng th = 8). . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 24 write to read: min. dqss, odd number of data (3 -bit write), interrupting (cl2; bl8) . . . . . . . . 49 figure 25 write to read: nominal dqss, in terrupting (cas latency = 2; burst length = 8) . . . . . . . . . . . . 50 figure 26 write to precharge: non-interrupting (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 27 write to precharge: interrupting (burst length = 4 or 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 28 write to precharge: minimum dqss, odd number of data (1-bit write), interrupting (bl 4 or 8). 53 figure 29 write to precharge: nominal dqss (2-bit write), interrupting (burst length = 4 or 8) . . . . . . . . . 54 figure 30 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 31 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 32 clock frequency change in pre charge power down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 33 simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 34 normal strength pull-down characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 35 normal strength pull-up characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 36 weak strength pull-down characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 37 weak strength pull-up characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 38 ac output load circuit diagram / timing reference load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 39 data input (write), timing burst length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 40 data output (read), timing burst length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 41 initialize and mode register sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 42 power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 43 auto refresh mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 44 self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 45 read without auto precharge (burst length = 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 46 read with auto precharge (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 47 bank read access (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 48 write without auto precharge (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 49 write with auto precharge (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 50 bank write access (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 51 write dm operation (burst length = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 52 pullup slew rate test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 53 pulldown slew rate test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 list of figures
data sheet 7 rev. 1.6, 2004-12 08012003-8754-paqx hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram figure 54 package outline of p-tfbga-60-12 (non-green/green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 55 package outline of p-tsopii-66-1 (non-green/green). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 list of figures
data sheet 8 rev. 1.6, 2004-12 08012003-8754-paqx hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram table 1 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2 ordering information for lead containing products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 table 3 ordering information for lead free (rohs compliant) prod ucts . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4 pin configuration of ddr sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7 burst definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9 truth table 1b: dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8 truth table 1a: commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 11 truth table 3: current state bank n - command to bank n (same bank) . . . . . . . . . . . . . . . . . . . 57 table 10 truth table 2: clock enable (cke) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 12 truth table 4: current state bank n - command to ba nk m (different bank). . . . . . . . . . . . . . . . . 59 table 13 truth table 5: concurrent auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 14 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 15 input and output capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 16 electrical characteristics and dc o perating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 table 18 evaluation conditions for i/o driver characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 17 normal strength pull-down and pull-up currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 19 weak strength driver pull-down and pull-up characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 20 ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 21 ac timing - absolute specifications for pc3200 and pc 2700 . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 22 ac timing - absolute specifications for pc2700 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 23 i dd conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 24 i dd specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 25 input slew rate for dq, dqs, and dm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 26 input setup & hold time derating for slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 27 input/output setup and hold time de rating for slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 28 input/output setup and hold derating for rise/fall de lta slew rate. . . . . . . . . . . . . . . . . . . . . . . 90 table 29 output slew rate characteristrics ( 4, 8 devices only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 30 output slew rate characteristics ( 16 devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 31 output slew rate matching ratio characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 32 tfbga common package properties (non-green/green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 list of tables
data sheet 9 rev. 1.6, 2004-12 256 mbit double-data-rate sdram ddr sdram hyb25d256[40/80/16]0ce(l) hyb25d256[40/80/16]0c[t/c/f] 1overview 1.1 features ? double data rate architecture: two data transfers per clock cycle ? bidirectional data strobe (dqs) is transmitted and rece ived with data, to be used in capturing data at the receiver ? dqs is edge-aligned with data for reads and is center-aligned with data for writes ? differential clock inputs (ck and ck ) ? four internal banks for concurrent operation ? data mask (dm) for write data ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? burst lengths: 2, 4, or 8 ? cas latency: 1.5 (ddr200 only), 2, 2.5, 3 ? auto precharge option for each burst access ? auto refresh and self refresh modes ? ras-lockout supported t rap = t rcd ?7.8 s maximum average periodic refresh interval ? 2.5 v (sstl_2 compatible) i/o ? v ddq = 2.5 v 0.2 v (ddr200, ddr266, ddr333); v ddq = 2.6 v 0.1 v (ddr400) ? v dd = 2.5 v 0.2 v (ddr200, ddr266, ddr333); v dd = 2.6 v 0.1 v (ddr400) ? p-tfbga-60-12 package with 3 depopulated rows (8 12 mm 2 ) ? p-tsopii-66 package ? lead- and halogene-free = green product table 1 performance part number speed code ?5 ?6 ?7 unit speed grade component ddr400b ddr333 ddr266a ? module pc3200-3033 pc2700?2533 pc2100-2033 ? max. clock frequency @cl3 f ck3 200 166 ? mhz @cl2.5 f ck2.5 166 166 143 mhz @cl2 f ck2 133 133 133 mhz
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram overview data sheet 10 rev. 1.6, 2004-12 1.2 description the 256 mbit double-data-rate sdram is a high-spe ed cmos, dynamic random-access memory containing 268,435,456 bits. it is internally configured as a quad-bank dram. the 256 mbit double-data-rate sdram uses a double-data-r ate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pi ns. a single read or write access for the 256 mbit double-data-rate sdram effe ctively consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide , one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is tran smitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the 256 mbit double-data-rate sdram operates from a differential clock (ck and ck ; the crossing of ck going high and ck going low is referred to as the positive edge of ck). commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to bot h edges of ck.read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coin cident with the active command are used to select the bank and row to be accessed. the address bits regist ered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or writ e burst lengths of 2, 4 or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdrams, the pipelined, multib ank architecture of ddr sdrams allows for concurrent operation, thereby providing high effective bandwidth by hiding ro w precharge and activation time. an auto refresh mode is provided along with a power-saving power-down mode. all inputs are compatible with the jedec standard for sstl_2. all outputs are sstl_2, class ii compatible. note: the functionality described and the timing specificatio ns included in this data sheet are for the dll enabled mode of operation. table 2 ordering information for lead containing products product type 2) org. cas-rcd-rp latencies clock (mhz) cas-rcd-rp latencies clock (mhz) speed package hyb25d256800ct?5 8 3-3-3 200 2.5-3-3 166 ddr400b p-tsopii-66 hyb25d256160ct?5 16 hyb25d256800ct?6 8 2.5-3-3 166 2-3-3 133 ddr333 hyb25d256800ct(l)?6 8 hyb25d256160ct?6 16 hyb25d256400ct?7 4 143 ddr266a hyb25d256400cc?5 4 3-3-3 200 2.5-3-3 166 ddr400b p-tfbga-60 hyb25d256800cc?5 8 hyb25d256160cc?5 16 hyb25d256400cc?6 4 2.5-3-3 166 2-3-3 133 ddr333 hyb25d256800cc?6 8 hyb25d256160cc?6 16
data sheet 11 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram overview table 3 ordering information for lead free (rohs 1) compliant) products 1) rohs compliant product: restriction of the use of certai n hazardous substances (rohs) in electrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include merc ury, lead, cadmium, hexavalent chro mium, polybrominated biphenyls and polybrominated biphenyl ethers. product type 2) 2) hyb: designator for memory components 25d: ddr sdrams at v ddq = 2.5 v 256: 256-mbit density 400/800/160: product variations 4, 8 and 16 c: die revision c l: low power (available on request) t/e/f/c: package type tsop(contains lead), tsop(lead & halo ne free), fbga(lead & halone free) and fbga (contains lead) org. cas-rcd-rp latencies clock (mhz) cas-rcd-rp latencies clock (mhz) speed package hyb25d256800ce?5a 8 2.5-3-3 200 2-3-3 133 ddr400a p-tsopii-66 hyb25d256160ce?5a 16 hyb25d256800ce?5 8 3-3-3 200 2.5-3-3 166 ddr400b hyb25d256160ce?5 16 hyb25d256800ce?6 8 2.5-3-3 166 2-3-3 133 ddr333 hyb25d256800ce(l)?6 8 hyb25d256160ce?6 16 hyb25d256400ce?7 4 143 ddr266a hyb25d256800cf?6 8 2.5-3-3 166 2-3-3 133 ddr333 p-tfbga-60
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram pin configuration data sheet 12 rev. 1.6, 2004-12 2 pin configuration the pin configuration of a ddr s dram is listed by function in table 4 (60 pins). the abbreviations used in the pin#/buffer# column are explained in table 5 and table 6 respectively. the pin numbering for fbga is depicted in figure 1 and that of the tsop package in figure 2 table 4 pin configuration of ddr sdram ball#/pin# name pin type buffer type function clock signals g2, 45 ck i sstl clock signal note: ck and ck are differential cloc k inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). g3, 46 ck i sstl complementary clock signal h3, 44 cke i sstl clock enable rank note: cke high activates, and cke low deactivates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks id le), or acti ve power-down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power- down. input buffers, excluding cke, are disabled during self refresh. cke is an sstl_2 input, but will detect an lvcmos low level after v dd is applied on first power up. after v ref has become stable during the power on and initialization sequence, it must be mantained for proper operation of the cke receiver. for proper self-refresh entry and exit, v ref must be mantained to this input. control signals h7, 23 ras i sstl row address strobe g8, 22 cas i sstl column address strobe g7, 21 we i sstl write enable h8, 24 cs i sstl chip select note: all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. the standard pinout includes one cs pin. address signals j8, 26 ba0 i sstl bank address bus 2:0 note: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. ba0 and ba1 also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. j7, 27 ba1 i sstl
data sheet 13 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram pin configuration k7, 29 a0 i sstl address bus 11:0 note: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the ba nk is selected by ba0, ba1. the address inputs also provide the op-code during a mode register set command. l8, 30 a1 i sstl l7, 31 a2 i sstl m8, 32 a3 i sstl m2, 35 a4 i sstl l3, 36 a5 i sstl l2, 37 a6 i sstl k3, 38 a7 i sstl k2, 39 a8 i sstl j3, 40 a9 i sstl k8, 28 a10 i sstl ap i sstl j2, 41 a11 i sstl h2, 42 a12 i sstl address signal 12 note: 256 mbit or larger dies nc nc ? note: 128 mbit or smaller dies f9, 17 a13 i sstl address signal 13 note: 1 gbit based dies nc nc ? note: 512 mbit or smaller dies data signals 4 organization b7, 5 dq0 i/o sstl data signal 3:0 d7, 11 dq1 i/o sstl d3, 56 dq2 i/o sstl b3, 62 dq3 i/o sstl data strobe 4 organisation e3, 51 dqs i/o sstl data strobe note: output with read data, input with write data. edge-aligned with read data, centered in wr ite data. used to capture write data. data mask 4 organization f3, 47 dm i sstl data mask: note: dm is an input mask signa l for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. table 4 pin configuration of ddr sdram ball#/pin# name pin type buffer type function
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram pin configuration data sheet 14 rev. 1.6, 2004-12 data signals 8 organization a8, 2 dq0 i/o sstl data signal 7:0 b7, 5 dq1 i/o sstl c7, 8 dq2 i/o sstl d7, 11 dq3 i/o sstl d3, 56 dq4 i/o sstl c3, 59 dq5 i/o sstl b3, 62 dq6 i/o sstl a2, 65 dq7 i/o sstl data strobe 8 organisation e3, 51 dqs i/o sstl data strobe note: output with read data, input with write data. edge-aligned with read data, centered in wr ite data. used to capture write data. data mask 8 organization f3, 47 dm i sstl data mask note: dm is an input mask signa l for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. data signals 16 organization a8, 2 dq0 i/o sstl data signal 15:0 b9, 4 dq1 i/o sstl b7, 5 dq2 i/o sstl c9, 7 dq3 i/o sstl c7, 8 dq4 i/o sstl d9, 10 dq5 i/o sstl d7, 11 dq6 i/o sstl e9, 13 dq7 i/o sstl e1, 54 dq8 i/o sstl d3, 56 dq9 i/o sstl d1, 57 dq10 i/o sstl c3, 59 dq11 i/o sstl c1, 60 dq12 i/o sstl b3, 62 dq13 i/o sstl b1, 63 dq14 i/o sstl a2, 65 dq15 i/o sstl data strobe 16 organization e3, 51 udqs i/o sstl data strobe upper byte e7, 16 ldqs i/o sstl data strobe lower byte data mask 16 organization table 4 pin configuration of ddr sdram ball#/pin# name pin type buffer type function
data sheet 15 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram pin configuration f3, 47 udm i sstl data mask upper byte f7, 20 ldm i sstl data mask lower byte power supplies f1, 49 v ref ai ? i/o reference voltage a9, b2, c8, d2, e8, 3, 9, 15, 55, 61 v ddq pwr ? i/o driver power supply a7, f8, m3, m7, 1, 18, 33 v dd pwr ? power supply a1, b8, c2, d8, e2, 6, 12, 52, 58, 64 v ssq pwr ? power supply f2, 34 v ss pwr ? power supply not connected a2, 65 nc nc ? not connected note: 4 organization a8, 2 nc nc ? not connected note: 4 organization b1, 63 nc nc ? not connected note: 8 and 4 organisation b9, 4 nc nc ? not connected note: 8 and 4 organization c1, 60 nc nc ? not connected note: 8 and 4 organization c3, 59 nc nc ? not connected note: 4 organization c7, 8 nc nc ? not connected note: 4 organization c9, 7 nc nc ? not connected note: 8 and 4 organization d1, 57 nc nc ? not connected note: 8 and 4 organization d9, 10 nc nc ? not connected note: 8 and 4 organization e1, 54 nc nc ? not connected note: 8 and 4 organization e7, 16 nc nc ? not connected note: 8 and 4 organization e9, 13 nc nc ? not connected note: 8 and 4 organization f7, 20 nc nc ? not connected note: 8 and 4 organization table 4 pin configuration of ddr sdram ball#/pin# name pin type buffer type function
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram pin configuration data sheet 16 rev. 1.6, 2004-12 f9, 14, 17, 19, 25,43, 50, 53 nc nc ? not connected note: 16 , 8 and 4 organization table 5 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected table 6 abbreviations for buffer type abbreviation description sstl serial stub terminated logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. table 4 pin configuration of ddr sdram ball#/pin# name pin type buffer type function
data sheet 17 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram pin configuration figure 1 pin configuration p-tfbga-60-9 top vi ew, see the balls throught the package , , ,
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram pin configuration data sheet 18 rev. 1.6, 2004-12 figure 2 pin configuration p-tsopii-66-1
data sheet 19 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram pin configuration figure 3 block diagram 16 mbit 4 i/o 4 internal memory banks row-address mux bank0 row-address latch & decoder bank control logic refresh counter address register receivers drivers read latch
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram pin configuration data sheet 20 rev. 1.6, 2004-12 figure 4 block diagram 8 mbit 8 i/o 4 internal memory banks row-address mux bank0 row-address latch & decoder bank control logic refresh counter address register receivers drivers read latch
data sheet 21 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram pin configuration figure 5 block diagram 4 mbit 16 i/o 4 internal memory banks row-address mux bank0 row-address latch & decoder bank control logic refresh counter address register receivers drivers read latch
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 22 rev. 1.6, 2004-12 3 functional description the 256 mbit double-data-rate sdram is a high-spe ed cmos, dynamic random-access memory containing 268,435,456 bits. the 256 mbit double-data-rate sdram is internally configured as a quad-bank dram. the 256 mbit double-data-rate sdram uses a double-data-r ate architecture to achieve high-speed operation. the double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o pi ns. a single read or write access for the 256 mbit double-data-rate sdram consists of a single 2n -bit wide, one clock cycle dat a transfer at the internal dram core and two corresponding n-bit wide, one-half clock cycle data transfers at the i/o pins. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a pr ogrammed sequence. accesses begin with the registration of an active command, which is th en followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0-a12 select the row). the address bits register ed coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the ddr sdram must be initia lized. the following sections provide detailed information covering device initialization, register defini tion, command descriptions and device operation. 3.1 initialization ddr sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined oper ation. the following cr iteria must be met: no power sequencing is specified during power up or power down given the following criteria: ? v dd and v ddq are driven from a single power converter output ? v tt meets the specification ? a minimum resistance of 42 ? limits the input current from the v tt supply into any pin and v ref tracks v ddq /2 or the following relation ship must be followed: ? v ddq is driven after or with v dd such that v ddq < v dd + 0.3 v ? v tt is driven after or with v ddq such that v tt < v ddq + 0.3 v ? v ref is driven after or with v ddq such that v ref < v ddq + 0.3 v the dq and dqs outputs are in the hi gh-z state, where they remain until driven in normal operation (by a read access). after all power supply an d reference voltages are stable, and the clock is stable, the ddr sdram requires a 200 s delay prior to applying an executable command. once the 200 s delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharg e all command should be applied. next a mode register set command should be issued for the extend ed mode register, to enable the dll, then a mode register set command should be issued for the mode regi ster, to reset the dll, and to program the operating parameters. 200 clock cycles are required between the dll reset and any executable command. during the 200 cycles of clock for dll locking, a deselect or nop command must be applied. after the 200 clock cycles, a precharge all command should be applied, pl acing the device in the ?all banks idle? state. once in the idle state, two auto refresh cycles mu st be performed. additionally, a mode register set command for the mode register, with the reset dll bit deact ivated (i.e. to program operating parameters without resetting the dll) must be perfo rmed. following these cycles, the ddr sd ram is ready for normal operation.
data sheet 23 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description 3.2 mode register definition the mode register is used to define the specific mode of operation of the ddr sdram. this definition includes the selection of a burst length, a burst type, a cas latency, and an operating mode. the mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit a8, which is self-clearing). mode register bits a0-a2 specify the burst length, a3 spec ifies the type of burst (sequential or interleaved), a4- a6 specify the cas latency, and a7-a12 specify the operating mode. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements results in unspecified operation. mr mode register definition (ba[1:0] = 00 b ) ba1ba0a12a11a10a9a8a7a6a5a4a3a2a1a0 0 0 operating mode cl bt bl reg. addr w w w w field bits type 1) 1) w = write only register bit description bl [2:0] w burst length number of sequential bits per dq related to one read/write command; see chapter 3.2.1 . note: all other bit combinations are reserved. 001 2 010 4 011 8 bt 3 burst type see table 7 for internal address sequence of low order address bits; see chapter 3.2.2 . 0 sequential 1 interleaved cl [6:4] cas latency number of full clocks from read comm and to first data valid window; see chapter 3.2.3 . note: all other bit combinations are reserved. 010 2 011 3 101 1.5 note: ddr200 components only 110 2.5 mode [12:7] operating mode see chapter 3.2.4 . note: all other bit combinations are reserved. 000000 normal operation without dll reset 000010 normal operation with dll reset
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 24 rev. 1.6, 2004-12 3.2.1 burst length read and write accesses to the ddr sdram are burst or iented, with the burst lengt h being programmable. the burst length determines the maximum number of column lo cations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are availabl e for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of column s equal to the burst length is effectively selected. all accesses for that burst take place within this block, mean ing that the burst wraps withi n the block if a boundary is reached. the block is uniquely selected by a1-ai when th e burst length is set to tw o, by a2-ai when the burst length is set to four and by a3-ai when the burst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. 3.2.2 burst type accesses within a given burst may be programmed to be eith er sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of acce sses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 7 . notes 1. for a burst length of two, a1-ai selects the two-data-ele ment block; a0 selects the first access within the block. 2. for a burst length of four, a2-ai selects the four-dat a-element block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-ai selects the eight-dat a- element block; a0-a2 selects the first access within the block. 4. whenever a boundary of the block is reached with in a given sequence above, the following access wraps within the block. table 7 burst definition burst length starting column address order of accesses within a burst a2 a1 a0 type = sequential type = interleaved 200-10-1 11-0 1-0 4 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 0000-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0011-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0102-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0113-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1004-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1015-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1106-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1117-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
data sheet 25 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description 3.2.3 read latency the read latency, or cas latency, is the delay, in clock cycles, between the registration of a read command and the availability of the first burst of output data. th e latency can be programmed 2, 2.5 and 3 clocks. cas latency of 1.5 is supported for ddr200 components only. if a read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m (see figure 6 ). reserved states should not be used as unknown operati on or incompatibility with futu re versions may result. 3.2.4 operating mode the normal operating mode is selected by issuing a mode register set command with bits a7-a12 set to zero, and bits a0-a6 set to the desired values. a dll reset is initiated by issuing a mode register set command with bits a7 and a9-a12 each set to zero, bit a8 set to one, and bits a0-a6 set to the desired values. a mode register set command issued to reset the dll should always be followed by a mode register set command to select normal operating mode. all other combinations of values for a7-a12 are rese rved for future use and/or test modes. test modes and reserved states should not be used as unknown operation or incompatibility wit h future versio ns may result. figure 6 required cas latencies nop nop nop nop nop read cas latency = 2, bl = 4 shown with nominal t ac , t dqsck , and t dqsq . ck ck command dqs dq don?t care cl=2 nop nop nop nop nop read cas latency = 2.5, bl = 4 ck ck command dqs dq cl=2.5
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 26 rev. 1.6, 2004-12 3.3 extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions include dll enable/disable, an d output drive strength selection (opt ional). these functions are controlled via the bits shown in the extended mo de register definition. the extended mode register is programmed via the mode register set command (with ba0 = 1 and ba1 = 0) and retains the stored information until it is programmed again or the device loses power. the extended mode regi ster must be loaded when all banks are idle, and the controller must wait the spec ified time before initiating any subsequent operation. violating either of these requirements result in unspecified operation. 3.3.1 dll enable/disable the dll must be enabled for normal operation. dll enab le is required during power up initialization, and upon returning to normal operation after having disabled the d ll for the purpose of debug or evaluation. the dll is automatically disabled when entering self refresh operat ion and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must oc cur before a read command can be issued. this is the reason 200 clock cycles must occur before issuing a read or write command upon exit of self refresh operation. 3.3.2 output drive strength the normal drive strength for all outputs is specified to be sstl_2, class ii. in addition this design version supports a weak driver mode for lighter load and/or po int-to-point environments which can be activated during mode register set. i - v curves for the normal and weak drive strength are included in this document. emr extended mode register definition (ba[1:0] = 01 b ) ba1ba0a12a11a10a9a8a7a6a5a4a3a2a1a0 0 1 operating mode ds dll reg. addr w w w field bits type 1) 1) w = write only register bit description dll 0w dll status see chapter 3.3.1 . 0 enabled 1 disabled ds 1 drive strength see chapter 3.3.2 , chapter 4.2 and chapter 4.3 . 0normal 1weak mode [12:2] operating mode note: all other bit combinations are reserved. 00000000000normal operation
data sheet 27 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description 3.4 commands deselect the deselect function prevents new commands from being executed by the ddr sdram. the ddr sdram is effectively deselected. operations al ready in progress are not affected. no operation (nop) the no operation (nop) command is used to perfo rm a nop to a ddr sdram. this prevents unwanted commands from being registered during idle or wait st ates. operations already in progress are not affected. mode register set the mode registers are loaded via inputs a0-a12, ba 0 and ba1. see mode register descriptions in chapter 3.2 . the mode register set command can only be issued when all banks are idle and no bursts are in progress. a subsequent executable comman d cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a12 selects the row. this row remains active (or open) for accesses until a precharge (or read or write with auto precharge) is issued to that bank. a precharge (or read or write with auto prec harge) command must be issued and completed before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-ai, aj (where [i = 8, j = don?t care] for x16, [i = 9, j = don?t care] for x8 and [i = 9, j = 11] for x4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the read burst; if auto precha rge is not selected, the row remains open for subsequent accesses. write the write command is used to initia te a burst write access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-ai, aj (where [i = 9, j = don?t care] for x8; where [i = 9, j = 11] for x4) selects the starti ng column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the write burst; if auto precharge is not selected, the row rema ins open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dm input lo gic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data is written to memory; if the dm signal is registered high, the corresponding data inputs are ignored, and a wr ite is not executed to that byte/column location. precharge the precharge command is used to deactivate (close) the ope n row in a particular bank or the open row(s) in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp ) after the precharge command is issued. input a10 determines whether one or a ll banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care?. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command is treated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging.
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 28 rev. 1.6, 2004-12 auto precharge auto precharge is a feature which performs the same in dividual-bank precharge func tions described above, but without requiring an explicit command. this is accomplished by using a 10 to enable auto precharge in conjunction with a specific read or write command. a precharge of th e bank/row that is addressed with the read or write command is automatically performed upon completion of th e read or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each in dividual read or write command. auto precharge ensures that the precharge is initiated at the ear liest valid stage within a burst. the us er must not issue another command to the same bank until the precharge ( t rp ) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in chapter 3.5 . burst terminate the burst terminate command is used to truncate read bur sts (with auto precharge disabled). the most recently registered read command prior to the burst te rminate command is truncated, as shown in chapter 3.5 . auto refresh auto refresh is used during normal operatio n of the ddr sdram and is analogous to cas before ras (cbr) refresh in previous dram types. this command is nonpersistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refr esh controller. this makes the address bits ?don?t care? during an auto refresh command. the 256 mbit double-data-rate sdram requires auto refresh cycles at an average periodic interval of 7.8 s (maximum). to allow for improv ed efficiency in scheduling and switching between tasks, some fl exibility in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted in the system, meaning that the maximum absolute interval between any auto refr esh command and the next auto refresh command is 9 7.8 s (70.2 s). this maximum absolute interv al is short enough to allow fo r dll updates internal to the ddr sdram to be restricted to auto refresh cycles, without allowing too much drift in t ac between updates. self refresh the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr sdram retains data without external clocking. the self refresh command is initiated as an auto refresh command coincident with cke transitioning low. the dll is automatically disabled upon entering self refresh, and is automatically enabled u pon exiting self refresh (200 clock cycles must then occur before a read command can be issued). input signals except cke (low) are ?don?t care? during self refresh oper ation.since cke is an sstl_2 input , v ref must be maintained during self refresh. the procedure for exiting self refresh requires a sequence of commands. ck (and ck ) must be stable prior to cke returning high. once cke is high, the sdram must have nop commands issued for t xsnr because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements is to apply nops for 200 clock cycles before applying any other command.
data sheet 29 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description table 8 truth table 1a: commands name (function) cs ras cas we address mne notes deselect (nop) h x x x x nop 1)2) no operation (nop) l h h h x nop 1)2) active (select bank and activate row) l l h h bank/row act 1)3) read (select bank and column, and start read burst) l h l h bank/col read 1)4) write (select bank and column, and start write burst) l h l l bank/col write 1)4) burst terminate l h h l x bst 1)5) precharge (deactivate row in bank or banks) l l h l code pre 1)6) auto refresh or self refresh (ent er self refresh mode) l l l h x ar/sr 1)7)8) mode register set l l l l op-code mrs 1)9) 1) cke is high for all commands shown except self refresh. v ref must be maintained during self refresh operation 2) deselect and nop are functionally interchangeable. 3) ba0-ba1 provide bank address and a0-a12 provide row address. 4) ba0, ba1 provide bank address; a0-ai provide column address (where i = 8 for x16, i = 9 for x8 and 9, 11 for x4); a10 high enables the auto precharge feature (nonpersi stent), a10 low disables the auto precharge feature. 5) applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled or for write bursts. 6) a10 low: ba0, ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0, ba1 are ?don?t care?. 7) this command is auto refresh if cke is high; self refresh if cke is low. 8) internal refresh counter controls row and bank addressi ng; all inputs and i/os are ?don?t care? except for cke. 9) ba0, ba1 select either the base or the extended mode r egister (ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserved; a0-a12 provide the op-code to be written to the selected mode register). table 9 truth table 1b: dm operation name (function) dm dqs notes write enable l valid 1) 1) used to mask write data; provided coincident with the corresponding data. write inhibit hx 1)
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 30 rev. 1.6, 2004-12 3.5 operations 3.5.1 bank/row activation before any read or write commands can be issued to a bank within the ddr sdram, a row in that bank must be ?opened? (activated). this is accomplished via the active command and addresses a0-a12, ba0 and ba1 (see figure 7 ), which decode and select both the bank and the row to be activated. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time inte rval between successive ac tive commands to the same bank is defined by t rc . a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total ro w-access overhead. the minimum time interval between successive active commands to different banks is defined by t rrd . figure 7 activating a specifi c row in a specific bank figure 8 t rcd and t rrd definition ra ba high ra = row address. ba = bank address. ck ck cke cs ras cas we a0-a12 ba0, ba1 don?t care row act nop col row ba y ba y ba x act nop nop ck ck command a0-a12 ba0, ba1 don?t care rd/wr t rcd t rrd rd/wr nop nop
data sheet 31 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description 3.5.2 reads subsequent to programming the mode register with cas latency, burst type, and burst length, read bursts are initiated with a read command, as shown on figure 9 . the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precha rge is enabled, the row that is accessed starts precharge at the completion of the burst, provided t ras has been satisfied. for the generic read commands used in the following illustration s, auto precharge is disabled.
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 32 rev. 1.6, 2004-12 during read bursts, the valid data-out element from th e starting column address is available following the cas latency after the read command. each subsequent data- out element is valid nominally at the next positive or negative clock edge (i.e. at the next crossing of ck and ck ). figure 10 shows general timing for each supported cas latency setting. dqs is driven by the ddr sdram al ong with output data. the initial low state on dqs is known as the read preamble; the low state coincident with the last data-out el ement is known as the read postamble. upon completion of a bu rst, assuming no other commands have been initiated, the dqs goes high-z. data from any read burst may be concatenated with or truncated with data from a subsequent read command. in either case, a continuous flow of data can be maintain ed. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burs t which is being truncated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architectu re). this is shown on figure 11 . a read command can be initiated on any clock cycle following a previous read command. nonconsecutive read data is illustrated on figure 12 . full-speed random read accesses: cas latencies (burst length = 2, 4 or 8) within a page (or pages) can be performed as shown on figure 13 .data from any read burst may be truncated with a burst terminate command, as shown on figure 14 . the burst terminate latency is equal to the read (cas) latency, i.e. the burst terminate command should be issued x cycles after the read command, where x equals the number of desired data element pairs. data from any read burst must be completed or trunca ted before a subsequent writ e command can be issued. if truncation is necessary, the burst terminate command must be used, as shown on figure 15 . the example is shown for t dqss(min) . the t dqss(max) case, not shown here, has a longer bus idle time. t dqss(min) and t dqss(max) are defined in chapter 3.5.3 . a read burst may be followed by, or truncated with, a pr echarge command to the same bank (provided that auto precharge was not activated). the precharge command should be issued x cycles after the read command, where x equals the number of desired data element pairs (p airs are required by the 2n prefetch architecture). this is shown on figure 16 for read latencies of 2 and 2.5. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data elements. in the case of a read being executed to completion , a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same read burst with auto precharge enabled. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts.
data sheet 33 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description figure 9 read command ba high ca = column address ba = bank address cke cs ras cas we a10 ba0, ba1 don?t care ca x4: a0-a9, a11 x8: a0-a9 en ap dis ap en ap = enable auto precharge dis ap = disable auto precharge ck ck x16: a0-a8
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 34 rev. 1.6, 2004-12 figure 10 read burst: cas latencies (burst length = 4) cas latency = 2 nop nop nop nop nop read ck ck command address dqs dq cas latency = 2.5 don?t care ba a,col n doa-n cl=2.5 nop nop nop nop nop read ck ck command address dqs dq ba a,col n doa-n do a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . cl=2
data sheet 35 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description figure 11 consecutive read bursts: cas latencies (burst length = 4 or 8) cas latency = 2 nop read nop nop nop read ck ck command address dqs dq cl=2 baa, col n baa, col b don?t care do a-n (or a-b) = data out from bank a, column n (or bank a, column b). when burst length = 4, the bursts are concatenated. when burst length = 8, the second burst interrupts the first. 3 subsequent elements of data out appear in the programmed order following do a-n. 3 (or 7) subsequent elements of data out appear in the programmed order following do a-b. shown with nominal t ac , t dqsck , and t dqsq . cas latency = 2.5 nop read nop nop nop read ck ck command address dqs dq cl=2.5 baa, col n baa,col b doa-n doa- n doa- b doa-b
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 36 rev. 1.6, 2004-12 figure 12 non-consecutive read bursts: cas latencies (burst length = 4) cas latency = 2 nop nop read nop nop read ck ck command address dqs dq do a-n doa- b do a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements of data out appear in the programme d order following do a-n (and following do a-b). shown with nominal t ac , t dqsck , and t dqsq . don?t care baa, col n baa, col b cl=2 cas latency = 2.5 nop nop read nop nop read do a-n doa- b baa, col n baa, col b cl=2.5 ck ck command address dqs dq nop
data sheet 37 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description figure 13 random read accesses: cas latencies (burst length = 2, 4 or 8) doa-n cas latency = 2 read read read nop nop read doa-b doa-n? doa-x doa-x? doa-b? doa-g ck ck command address dqs dq do a-n, etc. = data out from bank a, column n etc. n' etc. = odd or even complement of n, etc. (i.e., column address lsb inverted). reads are to active rows in any banks. shown with nominal t ac , t dqsck , and t dqsq . don?t care baa, col n baa, col x baa, col b baa, col g cl=2 cas latency = 2.5 read read read nop nop read ck ck command address dqs dq baa, col n baa, col x baa, col b baa, col g cl=2.5 doa-n doa-b doa-n? doa-x doa-x? doa-b?
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 38 rev. 1.6, 2004-12 figure 14 terminating a read burst: cas latencies (burst length = 8) cas latency = 2 nop bst nop nop nop read ck command address dqs dq do a-n = data out from bank a, column n. cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . doa-n don?t care ck baa, col n cl=2 cas latency = 2.5 nop bst nop nop nop read ck command address dqs dq doa-n ck baa, col n cl=2.5 no further output data after this point. dqs tristated. no further output data after this point. dqs tristated.
data sheet 39 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description figure 15 read to write: cas latencies (burst length = 4 or 8) cas latency = 2 bst nop write nop nop read di a-b ck ck command address dqs dq dm doa-n do a-n = data out from bank a, column n 1 subsequent elements of data out appear in the programmed order following do a-n. data in elements are applied following dl a-b in the programmed order, according to burst length. don?t care baa, col n baa, col b cl=2 t dqss (min) cas latency = 2.5 bst nop nop write nop read ck ck command address dqs dq dm doa-n baa, col n baa, col b cl=2.5 t dqss (min) dla-b shown with nominal t ac , t dqsck , and t dqsq . . di a-b = data in to bank a, column b
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 40 rev. 1.6, 2004-12 figure 16 read to precharge: cas latencies (burst length = 4 or 8) cas latency = 2 nop pre nop nop act read ck ck command address dqs dq doa-n do a-n = data out from bank a, column n. cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . don?t care ba a, col n ba a or all ba a, row cl=2.5 cas latency = 2.5 nop pre nop nop act read ck ck command address dqs dq doa-n t rp ba a, col n ba a or all ba a, row cl=2 t rp
data sheet 41 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description 3.5.3 writes write bursts are initiated with a write command, as shown in figure 17 . the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the gener ic write commands used in the follo wing illustrations, auto precharge is disabled. during write bursts, the first valid data-in element is regi stered on the first rising edge of dqs following the write command, and subsequent data elements are registered on successive edges of dqs. the low state on dqs between the write command and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time between the write command and the first corresponding rising edge of dqs ( t dqss ) is specified with a relatively wi de range (from 75% to 125% of one clock cycle), so most of the wr ite diagrams that follow are drawn for the two extreme cases (i.e. t dqss(min) and t dqss(max) ). figure 18 shows the two extremes of t dqss for a burst of four. upon completion of a burst, assuming no other commands have been initiated, the dqs and dqs enters high-z and any additional input data is ignored. data for any write burst may be concatenated with or trun cated with a subsequent write command. in either case, a continuous flow of input data can be maintained. th e new write command can be issued on any positive edge of clock following the previous write command. the first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burs t which is being truncated. the new write command should be issu ed x cycles after the first write command, where x equals the number of desired data element pairs (pairs are requ ired by the 2n prefetch architecture). figure 19 shows concatenated bursts of 4. an example of non- consecutive writes is shown in figure 20 . full-speed random write accesses within a page or pages can be performed as shown in figure 21 . data for any write burst may be followed by a subsequent read command. to follow a write without truncating the write burst, t wtr (write to read) should be met as shown in figure 22 . data for any write burst may be truncated by a subsequent read command, as shown in figure 23 to figure 25 . note that only the data-in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent data-in must be masked with dm, as shown in the diagrams noted previously. data for any write burst may be followed by a subsequent precharge command. to follow a write without truncating the write burst, t wr should be met as shown in figure 26 . data for any write burst may be truncated by a subsequent precharge command, as shown in figure 27 to figure 29 . note that only the data-in pairs that are registered prior to the t wr period are written to the internal array, and any subsequent data in should be masked with dm. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a write burst being executed to completi on, a precharge command issued at the optimum time (as described above) provides the same op eration that would result from the same burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts.
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 42 rev. 1.6, 2004-12 figure 17 write command ba high ca = column address ba = bank address cke cs ras cas we a10 ba0, ba1 don?t care ca x4: a0-a9, a11 x8: a0-a9 x16: a0-a8 en ap dis ap en ap = enable auto precharge dis ap = disable auto precharge ck ck
data sheet 43 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description figure 18 write burst (burst length = 4) t1 t2 t3 t4 t dqss (max) nop nop nop write di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. a10 is low with the write comm and (auto precharge is disabled). ck ck command address dqs dq dm don?t care maximum dqss ba a, col b t1 t2 t3 t4 t dqss (min) nop nop nop write ck ck command address dqs minimum dqss ba a, col b dq dm dla-b dla-b
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 44 rev. 1.6, 2004-12 figure 19 write to write (burst length = 4) t1 t2 t3 t4 t5 t6 t dqss (max) maximum dqss nop write nop nop nop write di a-b = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following di a-b. 3 subsequent elements of data in are applied in the programmed order following di a-n. a non-interrupted burst is shown. each write command may be to any bank. ck ck command address dqs dq dm don?t care t1 t2 t3 t4 t5 t6 minimum dqss nop write nop nop nop write ck ck command address dqs dq dm baa, col b baa, col n ba, col b ba, col n t dqss (min) di a-b di a-n di a-b di a-n
data sheet 45 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description figure 20 write to write: max. dqss, non-consecutive (burst length = 4) t1 t2 t3 t4 t5 t dqss (max) nop nop write nop write di a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following di a-b. 3 subsequent elements of data in are applied in the programmed order following di a-n. a non-interrupted burst is shown. each write command may be to any bank. ck ck command address dqs dq dm don?t care baa, col b baa, col n di a-b di a-n
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 46 rev. 1.6, 2004-12 figure 21 random write cycles (burst length = 2, 4 or 8) t1 t2 t3 t4 t5 t dqss (max) maximum dqss write write write write write di a-b di a-n di a-b, etc. = data in for bank a, column b, etc. b', etc. = odd or even complement of b, etc. (i.e., column address lsb inverted). each write command may be to any bank. di a-b? di a-x di a-x? di a-n? di a-a di a-a? ck ck command address dqs dq dm don?t care baa, col b baa, col x baa, col n baa, col a baa, col g t1 t2 t3 t4 t5 minimum dqss write write write write write di a-b di a-n di a-b? di a-x di a-x? di a-n? di a-a di a-a? ck ck command address dqs dq dm baa, col b baa, col x baa, col n baa, col a baa, col g t dqss (min) di a-g
data sheet 47 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description figure 22 write to read: non-interrupting (cas latency = 2; burst length = 4) cl = 2 t1 t2 t3 t4 t5 t6 t wtr nop nop nop read write di a-b nop di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. t wtr is referenced from the first positiv e ck edge after the last data in pair. a10 is low with the write comm and (auto precharge is disabled). the read and write commands may be to any bank. ck ck command address dqs dq dm don?t care maximum dqss baa, col b baa, col n t1 t2 t3 t4 t5 t6 t wtr nop nop nop read write nop ck ck command address minimum dqss baa, col b baa, col n t dqss (max) di a-b dqs dq dm t dqss (min) cl = 2
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 48 rev. 1.6, 2004-12 figure 23 write to read: interrupting (cas latency = 2; burst length = 8) t1 t2 t3 t4 t5 t6 t dqss (max) maximum dqss nop nop nop read write nop di a-b = data in for bank a, column b. an interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positive ck edge after the last data in pair. the read command masks the last 2 data elements in the burst. a10 is low with the write comm and (auto precharge is disabled). the read and write commands are not necessarily to the same bank. dia- b ck ck command address dqs dq dm don?t care baa, col b baa, col n t wtr cl = 2 t1 t2 t3 t4 t5 t6 minimum dqss nop nop nop read write nop ck ck command address baa, col b baa, col n t wtr di a-b dqs dq dm cl = 2 t dqss (min) 1 = these bits are incorrectly written into the memory array if dm is low. 11 11
data sheet 49 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description figure 24 write to read: min. dqss, odd number of data (3-bit write), interrupting (cl2; bl8) di a-b = data in for bank a, column b. an interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positive ck edge after the last desired data in pair (not the last desired data in element) the read command masks the last 2 data elements in the burst. a10 is low with the write comm and (auto precharge is disabled). the read and write commands are not necessarily to the same bank. don?t care t1 t2 t3 t4 t5 t6 nop nop nop read write nop ck ck command address baa, col b baa, col n t wtr di a-b dqs dq cl = 2 t dqss (min) dm 122 1 = this bit is correctly written into the memory array if dm is low. 2 = these bits are incorrectly written into the memory array if dm is low.
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 50 rev. 1.6, 2004-12 figure 25 write to read: nominal dqss, interrupting (cas latency = 2; burst length = 8) t1 t2 t3 t4 t5 t6 t dqss (nom) nop nop nop read write nop di a-b = data in for bank a, column b. an interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positive ck edge after the last desired data in pair. the read command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). the read and write commands are not necessarily to the same bank. di a-b ck ck command address dqs dq dm don?t care baa, col b baa, col n t wtr cl = 2 1 = these bits are incorrectly written into the memory array if dm is low. 1 1
data sheet 51 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description figure 26 write to precharge: non-interrupting (burst length = 4) t1 t2 t3 t4 t5 t6 t dqss (max) nop nop nop nop write di a-b pre di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. t wr is referenced from the first positive ck edge after the last data in pair. a10 is low with the write command (auto precharge is disabled). ck ck command address dqs dq dm don?t care ba a, col b ba (a or all) t wr maximum dqss t1 t2 t3 t4 t5 t6 nop nop nop nop write pre ck ck command address ba a, col b ba (a or all) t wr minimum dqss di a-b dqs dq dm t dqss (min) t rp t rp
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 52 rev. 1.6, 2004-12 figure 27 write to precharge: interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following di a-b. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst, for burst length = 8. a10 is low with the write command (auto precharge is disabled). 1 = can be don't care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don't care at this point. don?t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address maximum dqss di a-b 11 2 dqs dq dm t dqss (max) t rp t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) minimum dqss t wr t rp di a-b 11 dqs dq dm t dqss (min) 2 ba a, col b ba (a or all) t wr 3 = these bits are incorrectly written into the memory array if dm is low. 3 3 3 3
data sheet 53 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description figure 28 write to precharge: minimu m dqss, odd number of data (1-bit write), interrupting (bl 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 1 data element is written. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst. a10 is low with the write comm and (auto precharge is disabled). 1 = can be don't care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don't care at this point. don?t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) t wr t rp di a-b dqs dq t dqss (min) 2 11 dm 344 3 = this bit is correctly written in to the memory array if dm is low. 4 = these bits are incorrectly written into the memory array if dm is low.
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 54 rev. 1.6, 2004-12 figure 29 write to precharge: nominal dqss (2-bit write), interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following di a-b. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst. a10 is low with the write comm and (auto precharge is disabled). 1 = can be don't care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don't care at this point. don?t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) t rp t dqss (nom) di a-b 1 2 dqs dq dm 1 t wr 3 3 3 = these bits are incorrectly written into the memory array if dm is low.
data sheet 55 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description 3.5.4 precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. wh en all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care?. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. figure 30 precharge command ba high ba = bank address ck ck cke cs ras cas we a10 ba0, ba1 don?t care all banks one bank (if a10 is low, otherwise don?t care). a0-a9, a11, a12
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 56 rev. 1.6, 2004-12 3.5.5 power-down power-down is entered when cke is registered low (no accesses can be in progress). if power-down occurs when all banks are idle, this mode is referred to as precharge power-dow n; if power-down occurs when there is a row active in any bank, this mode is referred to as ac tive power-down. entering power-down deactivates the input and output buffers, excluding ck, ck and cke. the dll is still running in power down mode, so for maximum power savings, the user has the option of disabling the dll prior to entering power-down. in that case, the dll must be enabled afte r exiting power-down, and 200 clock cycles must occur before a read command can be issued. in power-down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr sdram, and all other input signals are ?don?t care?. however, power-down duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the dll-disabled power-down mode. the power-down state is synchronously exited when c ke is registered high (along with a nop or deselect command). a valid, executable command may be applied one clock cycle later. figure 31 power down t is t is ck ck cke command no column access in progress valid nop valid don?t care exit power down mode enter power down mode (burst read or write operation must not be in progress) nop
data sheet 57 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description note: 1. cken is the logic state of cke at clock edge n: c ke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr s dram immediately prior to clock edge n. 3. command n is the command registered at clock edge n, and action n is a result of command n. 4. all states and sequ ences not shown are illegal or reserved. table 10 truth table 2: clock enable (cke) current state cke n-1 cken command n action n notes previous cycle current cycle self refresh l l x main tain self-refresh 1) self refresh l h deselect or nop exit self-refresh 2) power down l l x maintain power-down ? power down l h deselect or nop exit power-down ? all banks idle h l deselect or no p precharge power-down entry ? all banks idle h l auto refresh self refresh entry ? bank(s) active h l deselect or nop active power-down entry ? hhsee table 11 ?? 1) v ref must be maintained during self refresh operation 2) deselect or nop commands should be issued on any cl ock edges occurring during the self refresh exit ( t xsnr ) period. a minimum of 200 clock cycles are needed before applying a read command to allow the dll to lock to the input clock. table 11 truth table 3: current state bank n - command to bank n (same bank) current state cs ras cas we command action notes any h x x x deselect nop. cont inue previous operation. 1)2)3)4)5)6) 1) this table applies when cke n-1 was high and cke n is high (see table 10 and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2) this table is bank-specific, except wher e noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. l h h h no operation nop. continue previous operation. 1) to 6) idle l l h h active select and activate row 1) to 6) lllhauto refresh? 1) to 7) llllmode register set ? 1) to 7) row active l h l h read select column and start read burst 1) to 6), 8) l h l l write select column and start write burst 1) to 6), 8) l l h l precharge deactivate row in bank(s) 1) to 6), 9) read (auto precharge disabled) l h l h read select column and start new read burst 1) to 6), 8) l l h l precharge truncate read burst, start precharge 1) to 6), 9) l hhl burst terminate burst terminate 1) to 6), 10) write (auto precharge disabled) l h l h read select column and start read burst 1) to 6), 8), 11) l h l l write select column and start write burst 1) to 6), 8) l l h l precharge truncate write burst, start precharge 1) to 6), 9), 11)
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 58 rev. 1.6, 2004-12 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4) the following states must not be interrupted by a command issued to the same bank. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ?row active? state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write w/auto precharge enabled: starts with registration of a write command wit h auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. deselect or nop commands, or allowable commands to the ot her bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and according to table 12 . 5) the following states must not be interrupted by any ex ecutable command; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rfc is met. once t rfc is met, the ddr sdram is in the ?all banks idle? state. accessing mode register: starts with registration of a mode register set command and ends when t mrd has been met. once t mrd is met, the ddr sdram is in the ?all banks idle? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks is in the idle state. 6) all states and sequences not shown are illegal or reserved. 7) not bank-specific; requires that all banks are idle. 8) reads or writes listed in the command/action column incl ude reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 9) may or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 10) not bank-specific; burst termin ate affects the most recent r ead burst, regardless of bank. 11) requires appropriate dm masking.
data sheet 59 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description table 12 truth table 4: current state bank n - command to bank m (different bank) current state cs ras cas we command action notes any h x x x deselect nop. continue previous operation. 1)2)3)4)5)6) l h h h no operation nop. continue previous operation. 1) to 6) idle xxxxany command otherwise allowed to bank m ? 1) to 6) row activating, active, or precharging l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to 7) l h l l write select column and start write burst 1) to 7) l l h l precharge ? 1) to 6) read (auto precharge disabled) l l h h active select and activate row 1) to 6) l h l h read select column and start new read burst 1) to 7) l l h l precharge ? 1) to 6) write (auto precharge disabled) l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to 8) l h l l write select column and start new write burst 1) to 7) l l h l precharge ? 1) to 6) read (with auto precharge) l l h h active select and activate row 1) to 6) l h l h read select column and start new read burst 1) to 7), 9) l h l l write select column and start write burst 1) to 7), 9), 10) l l h l precharge ? 1) to 6) write (with auto precharge) l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to 7), 9) l h l l write select column and start new write burst 1) to 7), 9) l l h l precharge ? 1) to 6) 1) this table applies when cke n-1 was high and cke n is high (see table 10 : clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2) this table describes alternate bank operation, except wher e noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read with auto precharge enabled: see 10) . write with auto precharge enabled: see 10) . 4) auto refresh and mode register set commands may only be issued when all banks are idle. 5) a burst terminate command cannot be issued to another bank; it applies to the bank repr esented by the current state only. 6) all states and sequences not shown are illegal or reserved.
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description data sheet 60 rev. 1.6, 2004-12 3.5.6 input clock frequency change ddr sdram input clock frequency cannot be changed duri ng normal operation. clock frequency change is only permitted during self refresh or during power down. in the latter case the following conditions must be met: ddr sdram must be in pre charged mode with cke at lo gic low level. after a minimum of 2 clocks after cke goes low, the clock frequency may change to any frequency between minimum and maximum operating frequeny specified for the particular speed grade. du ring an input clock frequency change, cke must be held low. once the input clock frequency is changed, a st able clock must be provided to dram before pre charge power down mode may be exited. the dll must be reset via emrs after pre charge power down exit. an additional mrs command may need to be issued to appropr iately set cl etc.. after t he dll relock time, the dram is ready to operate with the new clock frequency. figure 32 clock frequency change in pre charge power down mode 7) reads or writes listed in the command/action column incl ude reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8) requires appropriate dm masking. 9) concurrent auto precharge: this device supports ?concurrent auto precharge?. when a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not inte rrupt the read or write data transfer and all other limitations apply (e.g. contention be tween read data and write data must be avoided). the minimum delay from a read or write command with auto precharge enable, to a command to a different banks is summarized in table 13 . 10) a write command may be applied after the completion of data output. table 13 truth table 5: concurrent auto precharge from command to command (different bank) minimum delay with concurrent auto precharge support unit write w/ap read or read w/ap 1 + (bl/2) + t wtr t ck write to write w/ap bl/2 t ck precharge or activate 1 t ck read w/ap read or read w/ap bl/2 t ck write or write w/ap cl (rounded up) + bl/2 t ck precharge or activate 1 t ck
data sheet 61 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram functional description 3.6 simplified state diagram figure 33 simplified state diagram self auto idle mrs emrs row precharge power write power act read a read refs refsx refa ckel mrs ckeh ckeh ckel write power applied automatic sequence command sequence read a write a read pre pre pre pre refresh refresh down power down active on a read a read a write a burst stop preall active precharge precharge preall read write preall = precharge all banks mrs = mode register set emrs = extended mode register set refs = enter self refresh refsx = exit self refresh refa = auto refresh ckel = enter power down ckeh = exit power down act = active write a = write with autoprecharge read a = read with autoprecharge pre = precharge
data sheet 62 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics 4 electrical characteristics 4.1 operating conditions attention: permanent damage to the device may occu r if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operati on should be restricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. table 14 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq +0.5 v ? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) p d ?1.5? w? short circuit output current i out ?50? ma? table 15 input and output capacitances parameter symbol values unit note/ test condition min. typ. max. input capacitance: ck, ck c i1 1.5 ? 2.5 pf p-tfbga-60-12 1) 1) these values are not subject to production test - verified by design/characterization and are tested on a sample base only. vddq = vdd = 2.5 v 0.2 v, f = 100 mhz, ta = 25 c, vout (dc) = vddq/2, vout (peak to peak) 0.2 v. unused pins are tied to ground. 2.0 ? 3.0 pf p-tsopii-66 1) delta input capacitance c di1 ??0.25pf 1) input capacitance: all other input-only pins c i2 1.5 ? 2.5 pf p-tfbga-60-12 1) 2.0 ? 3.0 pf p-tsopii-66 1) delta input capacitance: all other input-only pins c dio ??0.5pf 1) input/output capacitance: dq, dqs, dm c io 3.5 ? 4.5 pf p-tfbga-60-12 1)2) 2) dm inputs are grouped with i/o pins reflecti ng the fact that they are matched in loading to dq and dqs to facilitate trace matching at the board level. 4.0 ? 5.0 pf p-tsopii-66 1)2) delta input/output capacitance: dq, dqs, dm c dio ??0.5pf 1)
data sheet 63 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics table 16 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) 1) 0 c t a 70 c min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck >166mhz 2) 2) ddr400 conditions apply for all clock frequencies above 166 mhz output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) 3) under all conditions, v ddq must be less than or equal to v dd . output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4) 4) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 5) 5) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . input high (logic1) voltage v ih(dc) v ref + 0.15 v ddq + 0.3 v 8) input low (logic0) voltage v il(dc) ?0.3 v ref ? 0.15 v 8) input voltage level, ck and ck inputs v in(dc) ?0.3 v ddq + 0.3 v 8) input differential voltage, ck and ck inputs v id(dc) 0.36 v ddq + 0.6 v 8)6) 6) v id is the magnitude of the differ ence between the input level on ck and the input level on ck . vi-matching pull-up current to pull-down current vi ratio 0.71 1.4 ? 7) 7) the ratio of the pull-up current to the pull-down current is specified for the sa me temperature and volt age, over the entire temperature and voltage range, for device drain to source volt age from 0.25 to 1.0 v. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test =0v 8)9) 8) inputs are not recognized as valid until v ref stabilizes. 9) values are shown per component output leakage current i oz ?5 5 a dqs are disabled; 0v v out v ddq output high current, normal strength driver i oh ? ?16.2 ma v out = 1.95 v output low current, normal strength driver i ol 16.2 ? ma v out = 0.35 v
data sheet 64 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics 4.2 normal strength pull-down and pull-up characteristics 1. the nominal pull-down v - i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v - i curve. 2. the full variation in driver pull-do wn current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v - i curve. 3. the nominal pull-up v - i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v - i curve. 4. the full variation in driver pull-up current from mi nimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v - i curve. 5. the full variation in the ratio of the maximum to mi nimum pull-up and pull-down current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain to source voltages from 0.1 to 1.0 v. figure 34 normal strength pull-down characteristics figure 35 normal strength pull-up characteristics 0 0.5 1 1.5 2 2.5 0 20 40 60 80 100 120 140 i out (ma) v ddq - v out (v) maximum nominal high nominal low minimum maximum nominal high nominal low minimum v ddq - v out (v) 0.5 1 1.5 2 2.5 0 0 -20 -40 -60 -80 -100 -120 -140 -160 i out (ma)
data sheet 65 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics table 17 normal strength pull-down and pull-up currents voltage (v) pulldown current (ma) pullup current (ma) nominal low nominal high min. max. nominal low nominal high min. max. 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 - 51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 - 51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 - 51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 - 51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 - 51.6 -124.0 -40.5 -156.9 2.1 62.9 99.1 49.6 126.5 - 51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 - 52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 - 52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 - 52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 - 52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 - 52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 - 52.8 -160.1 -41.2 -198.2 table 18 evaluation conditions for i/o driver characteristics parameter nominal minimum maximum operating temperature 25 c0 c70 c v dd / v ddq 2.5 v 2.3 v 2.7 v process corner typical slow-slow fast-fast
data sheet 66 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics 4.3 weak strength pull-down a nd pull-up characteristics 1. the weak pull-down v - i curve for ddr sdram devices is expected, bu t not guaranteed, to lie within the inner bounding lines of the v - i curve. 2. the weak pull-up v - i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v - i curve. 3. the full variation in driver pull-up current from mi nimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v - i curve. 4. the full variation in the ratio of the maximum to mi nimum pull-up and pull-down current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 5. the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain to source voltages from 0.1 to 1.0 v. figure 36 weak strength pull-down characteristics figure 37 weak strength pull-up characteristics 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 0 ,0 0 ,5 1 ,0 1 ,5 2 ,0 2 ,5 v o u t [v ] io u t [m a ] m a x im u m t y p ic a l h i g h t y p ic a l lo w m in im u m -8 0 ,0 -7 0 ,0 -6 0 ,0 -5 0 ,0 -4 0 ,0 -3 0 ,0 -2 0 ,0 -1 0 ,0 0 ,0 0 ,0 0 ,5 1 ,0 1 ,5 2 ,0 2 ,5 v o u t [ v ] io u t [ v ] m a x im u m t y p ic a l h ig h t y p ic a l lo w m in im u m
data sheet 67 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics table 19 weak strength driver pull-down and pull-up characteristics voltage (v) pulldown current (ma) pullup current (ma) nominal low nominal high min. max. nominal low nominal high min. max. 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 -6.9 -8.2 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6 0.6 19.6 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5 1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7 2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6 2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9 2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7
data sheet 68 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics 4.4 ac characteristics (notes 1-5 apply to the following tables; electrical c haracteristics and dc operatin g conditions, ac operating conditions, i dd specifications and conditions, and elec trical characterist ics and ac timing.) notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristi cs, may be conducted at nominal reference/ supply voltage levels, but the relate d specifications and device operation are guaranteed for the full voltage range specified. 3. figure 38 represents the timing reference load used in defi ning the relevant timing parameters of the part. it is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers will use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers w ill correlate to their production test conditions (generally a co axial transmission line terminated at the tester electronics). 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5 v in the test environment, but input timing is still referenced to v ref (or to the crossi ng point for ck, ck ), and parameter specific ations are guaranteed for the specified ac input levels under no rmal use conditions. the minimum slew rate for the input signals is 1 v/ ns in the range between v il(ac) and v ih(ac) . 5. the ac and dc input level specifications are as define d in the sstl_2 standard (i.e. the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc input low (high) level). 6. for system characteristics like setu p & holdtime derating for slew ra te, i/o delta rise/fall derating, ddr sdram slew rate standards, overshoot & undershoot specification and clamp v - i characteristics see the latest jedec specificat ion for ddr components. figure 38 ac output load circuit diagram / timing reference load 50 ? timing reference point output ( v out ) 30 pf v tt
data sheet 69 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics table 20 ac operating conditions 1) parameter symbol values unit note/ test condition min. max. input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.31 ? v 2)3) input low (logic 0) voltag e, dq, dqs and dm signals v il(ac) ? v ref ? 0.31 v 2)3) input differential voltage, ck and ck inputs v id(ac) 0.7 v ddq + 0.6 v 2)3)4) input closing point voltage, ck and ck inputs v ix(ac) 0.5 v ddq ? 0.2 0.5 v ddq + 0.2 v 2)3)5) 1) v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr200 - ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400); 0 c t a 70 c 2) input slew rate = 1 v/ns. 3) inputs are not recognized as valid until v ref stabilizes. 4) v id is the magnitude of the difference between t he input level on ck and the input level on ck . 5) the value of v ix is expected to equal 0.5 v ddq of the transmitting device and must tr ack variations in the dc level of the same. table 21 ac timing - absolute specifications for pc3200 and pc2700 parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max. dq output access time from ck/ck t ac ?0.5 +0.5 ?0.7 +0.7 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock cycle time t ck 5 8 6 12 ns cl = 3.0 2)3)4)5) 6 12 6 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck )+( t rp / t ck ) t ck 2)3)4)5)6) dq and dm input hold time t dh 0.4 ? 0.45 ? ns 2)3)4)5) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5)6) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.6 +0.6 ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.40 ns tfbga 2)3)4)5) ? +0.40 ? +0.45 ns tsopii 2)3)4)5) write command to 1 st dqs latching transition t dqss 0.72 1.25 0.75 1.25 t ck 2)3)4)5) dq and dm input setup time t ds 0.4 ? 0.45 ? ns 2)3)4)5)
data sheet 70 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )? min. ( t cl , t ch )? ns 2)3)4)5) data-out high-impedance time from ck/ck t hz ? +0.7 ?0.7 +0.7 ns 2)3)4)5)7) address and control input hold time t ih 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)9) address and control input setup time t is 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) data-out low-impedance time from ck/ck t lz ?0.7 +0.70 ?0.70 +0.70 ns 2)3)4)5)7) mode register set command cycle time t mrd 2?2? t ck 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs ? t hp ? t qhs ?ns 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.50 ns tfbga 2)3)4)5) ? +0.50 ? +0.55 ns tsopii 2)3)4)5) active to autoprecharge delay t rap t rcd ? t rcd ?ns 2)3)4)5) active to precharge command t ras 40 70e+3 42 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 55 ? 60 ? ns 2)3)4)5) active to read or write delay t rcd 15 ? 18 ? ns 2)3)4)5) average periodic refresh interval t refi ?7.8?7.8 s 2)3)4)5)8) auto-refresh to active/auto- refresh command period t rfc 70 ? 72 ? ns 2)3)4)5) precharge command period t rp 15 ? 18 ? ns 2)3)4)5) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active bank a to active bank b command t rrd 10 ? 12 ? ns 2)3)4)5) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)10) table 21 ac timing - absolute specifications for pc3200 and pc2700 parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max.
data sheet 71 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)11) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) internal write to read command delay t wtr 2?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) 1) 0 c t a 70 c ; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) for each of the terms, if not already an integer, round to the ne xt highest integer. t ck is equal to the actual system clock cycle time. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but sp ecify when the device is no longer driv ing (hz), or begins driving (lz). 8) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ ns, measured between v ih(ac) and v il(ac) . 9) these parameters guarantee device timing, but they are not necessarily tested on each device. 10) the specific requirement is th at dqs be valid (high,low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specificat ionsof the device. when no writes were previously in progress on the bus, dqs will be transitioning fr om hi-z to logic low. if a previous write was in progress, dqs could be high, low at this time, depending on t dqss . 11) the maximum limit for this parameter is not a device limit. the device operates with a greater value for th is parameter, but system performance (bus turnar ound) degrades accordingly. table 22 ac timing - absolute specifications for pc2700 parameter symbol ?7 unit note/test condition 1) ddr266a min. max. dq output access time from ck/ck t ac ?0.75 +0.75 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 t ck 2)3)4)5) clock cycle time t ck 7.5 12 ns cl = 3.0 3)4)5) 7.5 12 ns cl = 2.5 2)3)4)5) 7.5 12 ns cl = 2.0 2)3)4)5) ck low-level width t cl 0.45 0.55 t ck 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck )+( t rp / t ck )? t ck 2)3)4)5)6) dq and dm input hold time t dh 0.5 ? ns 2)3)4)5) dq and dm input pulse width (each input) t dipw 1.75 ? ns 2)3)4)5)6) table 21 ac timing - absolute specifications for pc3200 and pc2700 parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max.
data sheet 72 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics dqs output access time from ck/ck t dqsck ?0.75 +0.75 ns 2)3)4)5) dqs input low (high) pul se width (write cycle) t dqsl,h 0.35 ? t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ?+0.5nsfbga 2)3)4)5) ? +0.5 ns tsopii 2)3)4)5) write command to 1 st dqs latching transition t dqss 0.75 1.25 t ck 2)3)4)5) dq and dm input setup time t ds 0.5 ? ns 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )? ns 2)3)4)5) data-out high-impedance time from ck/ck t hz ?0.75 +0.75 ns 2)3)4)5)7) address and control input hold time t ih 0.9 ? ns fast slew rate 3)4)5)6)8) 1.0 ? ns slow slew rate 3)4)5)6)8) control and addr. input pulse width (each input) t ipw 2.2 ? ns 2)3)4)5)9) address and control input setup time t is 0.9 ? ns fast slew rate 3)4)5)6)8) 1.0 ? ns slow slew rate 3)4)5)6)8) data-out low-impedance time from ck/ck t lz ?0.75 +0.75 ns 2)3)4)5)7) mode register set command cycle time t mrd 2? t ck 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs ns 2)3)4)5) data hold skew factor t qhs ?0.75nsfbga 2)3)4)5) ? 0.75 ns tsopii 2)3)4)5) active to read w/ap delay t rap t rcd ?ns 2)3)4)5) active to precharge command t ras 45 120e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 65 ? ns 2)3)4)5) active to read or write delay t rcd 20 ? ns 2)3)4)5) average periodic refresh interval t refi 7.8 ? s 2)3)4)5)10) auto-refresh to ac tive/auto-refresh command period t rfc 75 ? ns 2)3)4)5) precharge command period t rp 20 ? ns 2)3)4)5) read preamble t rpre 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.4 0.6 t ck 2)3)4)5) active bank a to active bank b command t rrd 15 ? ns 2)3)4)5) write preamble t wpre 0.25 ? t ck 2)3)4)5) write preamble setup time t wpres 0?ns 2)3)4)5)11) table 22 ac timing - absolute specifications for pc2700 (cont?d) parameter symbol ?7 unit note/test condition 1) ddr266a min. max.
data sheet 73 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics write postamble t wpst 0.4 ? t ck 2)3)4)5)12) write recovery time t wr 15 ? ns 2)3)4)5) internal write to read command delay t wtr 1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ns 2)3)4)5)13) exit self-refresh to read command t xsrd 200 ? t ck 2)3)4)5) 1) v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v ; 0 c t a 70 c 2) input slew rate 1 v/ns 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) for each of the terms, if not already an integer, round to the ne xt highest integer. t ck is equal to the actual system clock cycle time. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but sp ecify when the device is no longer driv ing (hz), or begins driving (lz). 8) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ ns, measured between v ih(ac) and v il(ac) . 9) these parameters guarantee device timing, but they are not necessarily tested on each device. 10) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 11) the specific requirement is that dqs be valid (high, low, or some point on a vali d transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning fr om hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning fr om high to low at this time, depending on t dqss . 12) the maximum limit for this parameter is not a device limit. the device operates with a greater value for th is parameter, but system performance (bus turnar ound) degrades accordingly. 13) in all circumstances, t xsnr can be satisfied using t xsnr = t rfc,min +1 t ck table 22 ac timing - absolute specifications for pc2700 (cont?d) parameter symbol ?7 unit note/test condition 1) ddr266a min. max.
data sheet 74 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics table 23 i dd conditions parameter symbol operating current: one bank; active/ precharge; t rc = t rcmin ; t ck = t ckmin ; dq, dm, and dqs inputs changing once per clock cy cle; address and contro l inputs changing once every two clock cycles. i dd0 operating current: one bank; active/read/precharge; burst = 4; refer to the following page fo r detailed test conditions. i dd1 precharge power-down standby current: all banks idle; po wer-down mode; cke v ilmax ; t ck = t ckmin i dd2p precharge floating standby current: cs v ihmin , all banks idle; cke v ihmin ; t ck = t ckmin , address and other cont rol inputs changing once per clock cycle, v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current: cs v ihmin , all banks idle; cke v ihmin ; t ck = t ckmin , address and other control inputs stable at v ihmin or v ilmax ; v in = v ref for dq, dqs and dm. i dd2q active power-down standby current: one bank active; power-down mode; cke v ilmax ; t ck = t ckmin ; v in = v ref for dq, dqs and dm. i dd3p active standby current: one bank active; cs v ihmin ; cke v ihmin ; t rc = t rasmax ; t ck = t ckmin ; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. i dd3n operating current: one bank active; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data output s changing on every clock edge; cl = 2 for ddr200 and ddr266a, cl = 3 for ddr333; t ck = t ckmin ; i out =0ma i dd4r operating current: one bank active; burst = 2; writes; cont inuous burst; address and control inputs changing once per clock cycle; 50% of data output s changing on every clock edge; cl = 2 for ddr200 and ddr266a, cl = 3 for ddr333; t ck = t ckmin i dd4w auto-refresh current: t rc = t rfcmin , burst refresh i dd5 self-refresh current: cke 0.2 v; external clock on; t ck = t ckmin i dd6 operating current: four bank; four bank inte rleaving with bl = 4; refe r to the following page for detailed test conditions. i dd7
data sheet 75 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics 4.5 i dd current measur ement conditions legend: a = activate, r = read, ra = read with autoprecharge, p = precharge, n = nop or deselect i dd1 : operating current: one bank operation 1. general test condition a) only one bank is accessed with t rc,min . b) burst mode, address and control inputs are changing once per nop and deselect cycle. c) 50% of data changing at every transfer d) i out = 0 ma. 2. timing patterns a) ddr266a (133 mhz, cl = 2): t ck = 7.5 ns, bl = 4, t rcd = 3 t ck , t rc = 9 t ck , t ras = 5 t ck setup: a0 n n r0 n p0 n n n read: a0 n n r0 n p0 n nn - repeat the same timing with random address changing table 24 i dd specification symbol ?5 ?6 ?7 unit note/test condition 1) 1) test conditions for typical values: v dd = 2.5 v (ddr333), v dd = 2.6 v (ddr400), t a = 25 c, test conditions for maximum values: v dd = 2.7 v, t a = 10 c ddr400b ddr333 ddr266a typ. max. typ. max. typ. max. i dd0 70 90 60 75 50 65 ma 4/ 8 2)3) 2) i dd specifications are tested after the device is properly initialized and measured at 133 mhz for ddr266, 166 mhz for ddr333, and 200 mhz for ddr400. 3) input slew rate = 1 v/ns. 75 90 65 75 55 65 ma 16 3) i dd1 80 100 70 85 65 75 ma 4/ 8 3) 95 110 80 95 70 85 ma 16 3) i dd2p 4 5 4 5 3 4ma 3) i dd2f 30 36 25 30 20 24 ma 3) i dd2q 20 28 17 24 15 21 ma 3) i dd3p 13 18 11 15 9 13 ma 3) i dd3n 38 45 32 38 28 36 ma 3) 43 54 36 45 30 40 ma 16 3) i dd4r 85 100 70 85 60 70 ma 4/ 8 3) 100 120 85 100 70 85 ma 16 3) i dd4w 90 105 75 90 65 75 ma 4/ 8 3) 100 130 90 110 75 90 ma 16 3) i dd5 140 190 120 160 100 140 ma 3) i dd6 1.4 2.8 1.4 2.8 1.4 2.8ma 4) 4) enables on-chip refresh and address counters. ? ? 1.0 1.1 ? ? ma low power 5) 5) low power available on request i dd7 210 250 180 215 140 170 ma 4/ 8 3) 210 250 180 215 140 170 ma 16 3)
data sheet 76 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram electrical characteristics b) ddr333b (166 mhz, cl = 2.5): t ck = 6 ns, bl = 4, t rcd = 3 t ck , t rc = 9 t ck , t ras = 5 t ck setup: a0 n n r0 n p0 n n n read: a0 n n r0 n p0 n n n - repeat the same timing with random address changing c) ddr400b (200 mhz, cl = 3): t ck = 5 ns, bl = 4, t rcd = 3 t ck , t rc = 11 t ck , t ras = 8 t ck setup:a0 n n r0 n n n n p0 n n read: a0 n n r0 n n n n p0 n n -repeat the same timing with random address changing i dd7 : operating current: four bank operation 1. general test condition a) four banks are being interleaved with t rcmin . b) burst mode, address and control inputs on nop edge are not changing. c) 50% of data changing at every transfer d) i out = 0 ma. 2. timing patterns a) ddr266a (133 mhz, cl = 2): t ck = 7.5 ns, bl = 4, t rrd = 2 t ck , t rcd = 3 t ck , t ras = 5 t ck setup: a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 read: a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 - repe at the same timing with random address changing b) ddr333b (166 mhz, cl = 2.5): t ck = 6 ns, bl = 4, t rrd = 2 t ck , t rcd = 3 t ck , t ras = 5 t ck setup: a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 read: a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 - repe at the same timing with random address changing c) ddr400b (200 mhz, cl = 3): t ck = 5 ns, bl = 4, t rrd = 2 t ck , t rcd = 3 * t ck , t ras = 8 t ck setup: a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 n read: a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 n - repeat the same timing with random address
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram timing diagrams data sheet 77 rev. 1.6, 2004-12 5 timing diagrams the timing diagrams in this chapter give an overview of possible and recommended command sequences. 5.1 write command: data input timing figure 39 shows dqs versus dq and dm timing during write burst. figure 39 data input (write), timing burst length = 4 t dh t ds t dh t ds t dqsl di n = data in for column n. 3 subsequent elements of data in are applied in programmed order following di n. di n dqs dq dm don?t care t dqsh
data sheet 78 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram timing diagrams 5.2 read command: data output timing figure 40 shows dqs versus dq timing during read burst. figure 40 data output (read), timing burst length = 4 t qh (data output hold time from dqs) t dqsq and t qh are only shown once and are shown referenced to diffe rent edges of dqs, only for clarify of illustration. . dqs dq t dqsq max t qh t dqsq and t qh both apply to each of the four relevant edges of dqs. t dqsq max. is used to determine the worst case setup time for controller data capture. t qh is used to determine the worst case hold time for controller data capture.
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram timing diagrams data sheet 79 rev. 1.6, 2004-12 5.3 initialization and mode register set command figure 41 shows the timing diagram for init ialization and mode register sets. figure 41 initialize and mode register sets t ih 200 s t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t mrd t rfc t rfc t rp t mrd t mrd t cl t ck t ch t vtd pre emrs mrs pre ar ar mrs nop act code code code ra code code code ra ba0=l ba0=l ba high-z high-z power-up: vdd and ck stable extended mode register set load mode register, reset dll load mode register (with a8 = l) vdd vddq vtt (system * ) vref ck cke command dm a0-a9, a11 a10 ba0, ba1 dqs dq lvcmos low level all banks ba0=h ba1=l ba1=l ba1=l all banks * vtt is not applied directly to the device, however t vtd must be ** t mrd is required before any command can be applied and the two autorefresh commands may be moved to follow the first mrs, greater than or equal to zero to avoid device latchup. 200 cycles of ck are required before a read command can be applied. but precede the second precharge all command. don?t care 200 cycles of ck ** ck
data sheet 80 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram timing diagrams 5.4 power: power down mode command figure 42 shows the timing diagram for power down mode. figure 42 power down mode t ih t is t ih t is t is t is t ih t is t cl t ch t ck nop valid valid * valid valid enter power down mode exit power down mode no column accesses are allowed to be in progress at the time power down is entered. * = if this command is a precharge (or if the device is already in the idle state) then the power down mode shown is precharge power down. if this command is an ac tive (or if at least one row is already active), then the power down mode shown is active power down. cke command addr dqs dq dm don?t care c k c k nop
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram timing diagrams data sheet 81 rev. 1.6, 2004-12 5.5 refresh: auto refresh mode command figure 43 shows the timing diagram for auto refresh mode. figure 43 auto refresh mode t ih t is t ih t is t ih t is t rfc t rp t cl t ch t ck pre nop nop ar nop ar nop nop nop ra ra ba pre = precharge; act = active; ra = row address; ba = bank address; ar = autorefresh. nop commands are shown for ease of illustration; other valid commands may be possible at these times. dm, dq, and dqs signals are all don't care/high-z for operations shown. valid valid act ra cke command a0-a8 a9, a11,a12 a10 ba0, ba1 dqs dq dm bank(s) don?t care all banks one bank t rfc ck ck
data sheet 82 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram timing diagrams 5.6 refresh: self re fresh mode command figure 44 shows the timing diagram for self refresh mode. figure 44 self refresh mode 200 cycles t ih t is t xsrd, t xsrn t ih t is t is t is t ih t is t rp * t ck t cl t ch ar valid nop valid enter self refresh mode exit self refresh mode nop * = device must be in the all banks idle state before entering self refresh mode. ** = t xsnr is required before any non-read command can be applied, and t xsrd (200 cycles of ck). cke command addr dqs dq dm don?t care are required before a read command can be applied. ck ck clock must be stable before exiting self refresh mode
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram timing diagrams data sheet 83 rev. 1.6, 2004-12 5.7 read: without auto precharge command figure 45 shows the timing diagram for read without auto precharge. figure 45 read without auto precharge (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t ih t is t rp t cl t ch t ck pre nop nop act nop nop nop nop do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other commands may be valid at these times. ba x ba x valid valid valid nop read col n ra ra ba x * do n cke command a10 ba0, ba1 dm dqs dq dqs dq a0-a9, a11, a12 all banks one bank t dqsck (max) t rpre cl=2 t rpre don?t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n c k c k dis ap dis ap = disable auto precharge.
data sheet 84 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram timing diagrams 5.8 read: with auto precharge command figure 46 shows the timing diagram for read with auto precharge. figure 46 read with auto precharge (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t ih t is t rp t cl t ch t ck nop nop nop act nop nop nop nop do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. en ap = enable auto precharge. act = active; ra = row address. nop commands are shown for ease of illustration ; other commands may be valid at these times. ba x valid valid valid nop read col n ra ra do n cke command a10 ba0, ba1 dm dqs dq dqs dq a0-a9, a11, a12 t dqsck (max) t rpre cl=2 t rpre don?t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n en ap ba x c k c k t lz (min)
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram timing diagrams data sheet 85 rev. 1.6, 2004-12 5.9 read: bank read access command figure 47 shows the timing diagram for read bank read access. figure 47 bank read access (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t is t cl t ch t ck read nop pre nop nop act nop nop ba x ba x* valid nop act ra ra ba x do n c k c k cke command a10 ba0, ba1 dm dqs dq dqs dq t dqsck (max) t rpre cl=2 cl=2 t rpre don?t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n col n ra ra all banks ra one bank dis ap ba x t rp do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other commands may be valid at these times. t rcd a0-a9, a11, a12 t ras t rc t lz (min)
data sheet 86 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram timing diagrams 5.10 write: without au to precharge command figure 48 shows the timing diagram for write without auto precharge. figure 48 write without auto precharge (burst length = 4) t ih t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t ih t is t rp t cl t ch t ck nop nop nop pre nop nop act nop ba x ba nop write col n ra ra ba x * valid din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din. dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; ot her valid commands may be possible at these times. din c k c k cke command a10 ba0, ba1 dqs dq dm dis ap all banks one bank t wr t wpres t dqsh don?t care a0-a9, a11, a12 t dqss = min. t dqss t wpre t dsh
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram timing diagrams data sheet 87 rev. 1.6, 2004-12 5.11 write: with auto precharge command figure 49 shows the timing diagram for write with auto precharge. figure 49 write with auto precharge (burst length = 4) nop commands are shown for ease of illustration; other valid commands may be possible at these times. act = active; ra = row address; ba = bank address. t ih t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t is t rp t cl t ch t ck nop nop nop nop nop nop act nop ba x ba nop write col n ra ra valid din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din. en ap = enable auto precharge. c k c k cke command a10 ba0, ba1 dqs dq dm t wr t dqss t wpres t dqsh don?t care valid valid en ap a0-a9, a11, a12 t dal t dqss = min. t dsh t wpre din
data sheet 88 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram timing diagrams 5.12 write: bank wr ite access command figure 50 shows the timing diagram for bank write access. figure 50 bank write access (burst length = 4) t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t ih t is t cl t ch t ck t ras write nop nop nop nop pre nop nop ba x nop act ra ra di n = data in for column n. 3 subsequent elements of data in are appli ed in the programmed order following di n. dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address. nop commands are shown for ease of illustration; ot her valid commands may be possible at these times. din valid ba x cke command a10 ba0, ba1 dqs dq dm ck ck t wpres t wr t rcd all banks one bank dis ap don?t care a0-a9, a11, a12 col n ba x t dqss t dqsh t dsh t wpre t dqss = min.
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram timing diagrams data sheet 89 rev. 1.6, 2004-12 5.13 write: dm operation figure 51 shows the timing diagram for dm operation. figure 51 write dm operation (burst length = 4) t ih t wpst t dqsl t ih t is t ih t is t is t rp t cl t ch t ck nop nop nop pre nop nop act nop nop write col n ra din ck ck cke command a10 ba0, ba1 dqs dq dm t wr t dqss don?t care valid t ih t is t ih t is ba x ba ra ba x * all banks one bank dis ap di n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following di n (the second element of the 4 is masked). dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; ot her valid commands may be possible at these times. a0-a9, a11, a12 t dqsh t dsh t dqss = min. t wpres
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram system characteristics for ddr sdrams data sheet 90 rev. 1.6, 2004-12 08012003-8754-paqx 6 system characteristics for ddr sdrams the following specification parameters are required in systems using ddr400, ddr333 & ddr266 devices to ensure proper system performance. these characteristics are for system simulation purposes and are not subject to production test - verified by design/characterization. table 25 input slew rate for dq, dqs, and dm ac characteristics symbol ddr 400 ddr333 ddr266 units notes parameter min. max. min. max. min. max. dm/dqs inout slew rate measured berween v ih(dc) , v il (dc) , and v il(dc) , v ih (dc) dcslew 0.5 4.0 0.5 4.0 0.5 4.0 v/ns 1)2) 1) pullup slew rate is characterized under the test conditions as shown in figure 52 . 2) dqs, dm, amd dq input slew rate is specified to prevent d oble clocking of data and preserve setup and hold times. signal transitions through the dc region must be monotonic. table 26 input setup & hold time derating for slew rate input slew rate ? t is t ih units notes 0.5 v/ns 0 0 ps 1) 1) a derating factor will be used to increase t is and t ih in the case where the input slew rate is below 0.5 v/ns as shown in table 26 . the input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc), similarly for rising transitions. aderating fa ctor applies to speed bins ddr200, ddr266, and ddr333. 0.4 v/ns +50 0 ps 0.3 v/ns +100 0 ps table 27 input/output setup and hold time derating for slew rate i/o input slew rate ? t ds t dh units notes 0.5 ns/v 0 0 ps 1) 1) table 27 is used to increase t ds and t dh in the case where the i/o slew rate is below 0.5 v/ns. the i/o slew rate is based on the lesser of the av ? ac slew rate and the dc ? dc slew rate. the input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc), and similarly for rising transitions. a derating factor applies to speed bins ddr200, ddr266 and ddr333. 0.4 ns/v +75 +75 ps 0.3 ns/v +100 +100 ps table 28 input/output setup and hold derating for rise/fall delta slew rate delta slew rate ? t ds t dh units notes 0.0 ns/v 0 0 ps 1) 1) a derating factor will be used to increase t ds and t dh in the case where dq, dm and dqs slew rates differ, as shown in figure 27 & figure 28 . input slew rate is based on the larger of ac ? ac delta rise, fall rate and dc ? dc delta rise, fall rate. input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc), similarly for rising transitions. the delta rise/fall rate is calculated as:{1/(slew rate1)} ? {1/(slew rate2)} for example: if slew rate 1 is 0.5 v/ns and slew rate 2 is 0.4 v/ns, then the delta rise, fall rate is ?0.5 ns/v. using the table given, this would result in the need for an increase in t ds and t dh of 100 ps. a derating factor applies to speed bins ddr200, ddr266, and ddr333. 0.25 ns/v + 50 + 50 ps 0.5 ns/v + 100 + 100 ps
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram system characteristics for ddr sdrams data sheet 91 rev. 1.6, 2004-12 08012003-8754-paqx figure 52 pullup slew rate test load figure 53 pulldown slew rate test load table 29 output slew rate characteristrics ( 4, 8 devices only) slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ? 2.5 1.0 4.5 1)2)3)4)5)6) pulldown slew rate 1.2 ? 2.5 1.0 4.5 2)3)4)5)7) table 30 output slew rate characteristics ( 16 devices only) slew rate characteristic typical range (v/ns) minimum (v/ns) maximum(v/ns) notes pullup slew rate 1.2 ? 2.5 0.7 5.0 1)2)3)4)5)6) 1) pullup slew rate is characterizted un der the test conditions as shown in figure 52 2) pullup slew rate is measured between ( v ddq /2 ? 320 mv 250 mv) pulldown slew rate is measured between ( v ddq /2 + 320 mv 250mv) pullup and pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching.example: for typical slew rate, dq0 is switching.for minimum slew rate, all dq bits are switchiung worst case pattern. for maximum slew rate, only one dq is switching from either high to low, or low to high the remainig dq bits remain the same as previous state. 3) evaluation conditions: typical: 25 c (t ambient), v ddq = nominal, typical process.minimum: 70 c (t ambient), v ddq = minimum, slow ? slow process. maximum: 0 c (t ambient), v ddq = maximum, fast ? fast process 4) verified under typical conditions for qualification purposes. 5) tsop ii package devices only. 6) only intended for operation up to 266 mbps per pin. pulldown slew rate 1.2 ? 2.5 0.7 5.0 2)3)4)5)7) 7) pulldown slew rate is measured under the test conditions shown in figure 53 . table 31 output slew rate matching ratio characteristics slew rate characteristic ddr266a ddr266b ddr200 notes parameter min. max. min. max. min. max. output slew rate matching ratio (pullup to pulldown) ? ? ? ? 0.71 1.4 1) 2) 1) the ratio of pullup slew rate to pulldown slew rate is sp ecified for the same temperatur e and voltage, over the entire temperature and voltage range. for a gi ven output, it represents the maximum difference between pullup and pulldown drivers due to process variation. 2) dqs, dm, and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal transitions through the dc region must be monotonic
data sheet 92 rev. 1.6, 2004-12 hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram package outlines 7 package outlines there are two package types used for this product fam ily each in lead-free and lead-containing assembly: ? p-tfbga: plastic thin fine-p itch ball grid array package figure 54 package outline of p-tfbga-60-12 (non-green/green) table 32 tfbga common package properties (non-green/green) description size units ball size 0.460 mm recommended landing pad 0.350 mm recommended solder mask 0.450 mm gpa0955 5 5 ) middle of packages edges 4 ) bad unit marking (bum) 2 ) a1 marking chipside 1 ) a1 marking ballside 3 ) dummy pads without ball 11 x 1 = 11 1 1.8 max. 8 x 0.8 = 6.4 0.8 b 5) 1) a 3) 4) 0.18 ma x. 0.05 2 ) 1.2 max. 0.31 min. 12 2.24 8 4.25 2) 1.5 0.2 0.1 c 0.05 ?0.46 ?0.08 ?0.15 60x m m a c b seating plane 0.1 c c 5)
hyb25d256[16/40/80]0c[e/c/f/t](l) 256 mbit double-data-rate sdram package outlines data sheet 93 rev. 1.6, 2004-12 ? p-tsopii: plastic thin sma ll outline package type ii figure 55 package outline of p-tsopii-66-1 (non-green/green) gpx09261 0.65 basic 0.35 +0.1 -0.05 0.805 ref 0.05 min. 1.20 max. 22.22 lead 1 10.16 0.5 11.76 0.1 0.25 basic gage plane seating plane 0.13 0.2 0.13 0.1
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